As digital data processing technology continues to improve, the need for higher data transmission rates continues to increase. For example, the IEEE 25 Gigabit Ethernet standard IEEE 802.3by provides for a single-lane bit rate greater than 25 Gbit/s. Achieving such high data rates is very challenging due to performance limitations of the physical media and silicon-based transceiver circuits. This challenge has led to the development of special purpose, high-speed serializer and de-serializer (“SerDes”) integrated circuit (“IC”) modules that convert parallel, on-chip, bit streams into multigigabit-per-second serial bit streams for off-chip communications, and back again on the receiving end. Such SerDes modules are available for incorporation into the IC designs of networking and interface device manufacturers.
Due to interference, the high-rate serial bit stream signals may suffer relatively high bit error rates (e.g., 10−5), as compared with a typical target value (e.g., 10−12). Forward error correction (FEC) offers many codes and coding techniques that enable the target error rate to be achieved, yet the makers of SerDes modules are typically unable to specify coding requirements for the users of such modules. Moreover, they may be limited in their ability to specify minimum performance characteristics of the physical communications link. This situation, together with the multitude of configuration parameters for the link and the FEC code, may make it difficult for potential users of SerDes modules to judge their suitability.